The present invention relates generally to a low-cost method for fabricating devices and integrated circuits with reduced cross-sectional area, and more specifically to a low-cost method for fabricating a static random access memory (SRAM) having reduced cross-sectional area.
Electronics technology has proliferated with the advent of inexpensive and high performance integrated circuits, including communication transceivers, microprocessors, and memory. As a result, complex electronic systems, such as personal computers and cellular telephones have become widely held consumer goods.
Integrated circuits are fabricated with multiple processing steps. Integrated circuits are often fabricated with one or more device types including diodes, capacitors, and different varieties of transistors. These devices often have microscopic features that can only be manufactured with critical processing steps that require careful alignment of equipment used to build the devices. The critical processing steps are expensive because they must be accomplished with costly and sophisticated equipment, and experienced operators. When a processing step, particularly a critical processing step, is unsuccessful, the device and integrated circuit may fail. As a result, fabrication yields decrease. Therefore, a process with a diminished number of critical processing steps to reduce production costs is desirable.
Further, prior art typically uses Buried Contacts (BC) that connect a first conductor to substrate active area. The BC process however is a lower yielding process than the self aligned contacts described herein. In addition, BC""s require full enclosure by the first conductor which requires additional area, thereby increasing the cell size.
Additionally, it is preferable to reduce the cross-sectional area of devices and integrated circuits. When device and integrated circuit cross-sectional area is reduced, more devices and integrated circuits can be produced on a single substrate. As a result, device and integrated circuit fabrication costs decrease. Therefore, a low cost process with fewer critical processing steps for fabricating devices and integrated circuits with reduced cross-sectional areas is desirable. An integrated circuit is also needed which electrically couples substrate active area with a conductor without the need for a buried contact.
In accordance with the present invention, there is provided a method of fabricating devices having smaller cross-sectional areas with fewer critical processing steps. One embodiment of the present invention permits fabrication of an SRAM with fewer processing steps. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings.
A static random access memory (SRAM) device is described which comprises a self-aligned electrical contact to semiconductor active area and a second electrical contact to a non-active area electrically conductive structure. The self-aligned electrical contact and the second electrical contact are defined by a process comprising a single dielectric etch step.
In another embodiment, a method of fabricating electrical interconnects in a static random access memory (SRAM) cell is described. The method comprises the steps of forming first and second dielectric-conductor-dielectric layered structures, and a dielectric-conductor layered structure on a semiconductive base. Vertical dielectric structures are formed and attach to exposed vertical surfaces of the first and second dielectric-conductor-dielectric structures and the dielectric-conductor structure. A dielectric layer is formed over the first and second dielectric-conductor-dielectric structures, the dielectric-conductor structure, and exposed semiconductive base between the first and second structures. A single etch step is performed on the dielectric layer to define a self aligned contact to the semiconductive base located between the first and second dielectric-conductor-dielectric structures, and a contact to the conductor of the dielectric-conductor structure.